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256/512/1k/2k/4k x 9 asynchronous fifo cy7c419/21/25/29/33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06001 rev. ** revised november 4, 1997 19/21/25/29/ features ? asynchronous first-in first-out (fifo) buffer memories 256 x 9 (cy7c419) 512 x 9 (cy7c421) 1k x 9 (cy7c425) 2k x 9 (cy7c429) 4k x 9 (cy7c433) dual-ported ram cell high-speed 50.0-mhz read/write independent of depth/width low operating power: i cc = 35 ma empty and full flags (half full flag in standalone) ttl compatible retransmit in standalone expandable in width plcc, 7x7 tqfp, soj, 300-mil and 600-mil dip pin compatible and functionally equivalent to idt7200, idt7201, idt7202, idt7203, idt7204, am7200, am7201, am7202, am7203, and am7204 functional description the cy7c419, cy7c420/1, cy7c424/5, cy7c428/9, and cy7c432/3 are first-in first-out (fifo) memories offered in 600-mil wide and 300-mil wide packages. they are, respec- tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide. each fifo memory is organized such that the data is read in the same sequential order that it was written. full and empty flags are provided to prevent overrun and underrun. three ad- ditional pins are also provided to facilitate unlimited expansion in width, depth, or both. the depth expansion technique steers the control signals from one device to another in parallel, thus eliminating the serial addition of propagation delays, so that throughput is not reduced. data is steered in a similar manner. the read and write operations may be asynchronous; each can occur at a rate of 50.0 mhz. the write operation occurs when the write (w ) signal is low. read occurs when read (r ) goes low. the nine data outputs go to the high-impedance state when r is high. a half full (hf ) output flag is provided that is valid in the stan- dalone and width expansion configurations. in the depth ex- pansion configuration, this pin provides the expansion out (xo ) information that is used to tell the next fifo that it will be activated. in the standalone and width expansion configurations, a low on the retransmit (rt ) input causes the fifos to retransmit the data. read enable (r ) and write enable (w ) must both be high during retransmit, and then r is used to access the data. the cy7c419, cy7c420, cy7c421, cy7c424, cy7c425, cy7c428, cy7c429, cy7c432, and cy7c433 are fabricated using an advanced 0.65-micron p-well cmos technology. in- put esd protection is greater than 2000v and latch-up is pre- vented by careful layout and guard rings.
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 2 of 22 maximum rating (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high z state................................................ ? 0.5v to +7.0v dc input voltage ............................................ ? 0.5v to +7.0v power dissipation.......................................................... 1.0w output current, into outputs (low)............................ 20 ma static discharge voltage ........................................... >2000v (per mil ? std ? 883, method 3015) latch-up current..................................................... >200 ma ram array 256 x 9 512 x 9 1024x 9 2048x 9 4096x 9 logic block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 24 23 22 21 13 14 25 28 27 26 top view dip 7c420/1 w d 8 d 3 d 2 d 1 d 0 xi ff q 0 q 1 q 2 gnd v cc d 4 fl /rt mr ef xo /hf q 7 r plcc/lcc top view q 3 q 8 d 5 d 6 d 7 q 6 q 5 q 4 4 3 2 1 323130 14 15 1617 181920 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 fl /rt mr ef xo /hf q 7 d 6 q 6 d 7 nc read control write control write pointer reset logic expansion logic data inputs (d 0 ? d 8 ) three- state buffers data outputs (q 0 ? q 8 ) w read pointer flag logic r xi ef ff xo/hf mr fl /rt d 2 d 1 d 0 xi ff q 0 q 1 nc q 2 d d w nc v d d 3 8 cc 4 5 q q gnd nc r q q 3 8 4 5 c420 ? 1 c420 ? 2 c420 ? 3 7c419 7c421/5/9 7c433 7c424/5 7c428/9 7c432/3 7c419 26 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 101112131415 32 3130 29 28 27 25 q 1 xi q 0 d 1 d 0 nc nc ff d 6 d 5 d 4 v cc w d 8 d 3 d 2 d 7 fl/rt nc nc mr ef xo/hf q 7 c420 ? 4 top view tqfp q 2 q 3 q 8 gnd r q 4 q 5 q 6 16 7c419 7c421/5/9 7c433 selection guide 256 x 9 7c419 ? 10 7c419 ? 15 7c419 ? 30 7c419 ? 40 512 x 9 (600-mil only) 7c420 ? 20 7c420 ? 25 7c420 ? 40 7c420 ? 65 512 x 9 7c421 ? 10 7c421 ? 15 7c421 ? 20 7c421 ? 25 7c421 ? 30 7c421 ? 40 7c421 ? 65 1k x 9 (600-mil only) 7c424 ? 20 7c424 ? 25 7c424 ? 30 7c424 ? 40 7c424 ? 65 1k x 9 7c425 ? 10 7c425 ? 15 7c425 ? 20 7c425 ? 25 7c425 ? 30 7c425 ? 40 7c425 ? 65 2k x 9 (600-mil only) 7c428 ? 20 7c428 ? 65 2k x 9 7c429 ? 10 7c429 ? 15 7c429 ? 20 7c429 ? 25 7c429 ? 30 7c429 ? 40 7c429 ? 65 4k x 9 (600-mil only) 7c432 ? 25 7c432 ? 40 4k x 9 7c433 ? 10 7c433 ? 15 7c433 ? 20 7c433 ? 25 7c433 ? 30 7c433 ? 40 7c433 ? 65 frequency (mhz) 50 40 33.3 28.5 25 20 12.5 maximum access time (ns) 10 15 20 25 30 40 65 i cc1 (ma) 35 35 35 35 35 35 35
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 3 of 22 operating range range ambient temperature [1] v cc commercial 0 c to + 70 c 5v 10% industrial ? 40 c to +85 c 5v 10% military ? 55 c to +125 c 5v 10% electrical characteristics over the operating range [2] 7c419 ? 10, 15, 30, 40 7c420/1 ? 10, 15, 20, 25, 30, 40, 65 7c424/5 ? 10, 15, 20, 25, 30, 40, 65 7c428/9 ? 10, 15, 20, 25, 30, 40, 65 7c432/3 ? 10, 15, 20, 25, 30, 40, 65 parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage com ? l 2.0 v cc v mil/ind 2.2 v cc v il input low voltage note 3 0.8 v i ix input leakage current gnd < v i < v cc ? 10 +10 a i oz output leakage current r > v ih , gnd < v o < v cc ? 10 +10 a i os output short circuit current [4] v cc = max., v out = gnd ? 90 ma electrical characteristics over the operating range [2] (continued) 7c419 ? 10 7c421 ? 10 7c425 ? 10 7c429 ? 10 7c433 ? 10 7c419 ? 15 7c421 ? 15 7c425 ? 15 7c429 ? 15 7c433 ? 15 7c420 ? 20 7c421 ? 20 7c424 ? 20 7c425 ? 20 7c428 ? 20 7c429 ? 20 7c433 ? 20 7c420 ? 25 7c421 ? 25 7c424 ? 25 7c425 ? 25 7c429 ? 25 7c432 ? 25 7c433 ? 25 parameter description test conditions min. max. min. max. min. max. min. max. unit i cc operating current v cc = max., i out = 0 ma f = f max com ? l 85 65 55 50 ma mil/ind 100 90 80 i cc1 operating current v cc = max., i out = 0 ma f = 20 mhz com ? l 35 35 35 35 ma i sb1 standby current all inputs = v ih min. com ? l 10 10 10 10 ma mil/ind 15 15 15 i sb2 power-down current all inputs > v cc ? 0.2v com ? l 5 5 5 5 ma mil/ind 8 8 8 notes: 1. t a is the ? instant on ? case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 4. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 sec onds.
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 4 of 22 electrical characteristics over the operating range [2] (continued) 7c419 ? 30 7c421 ? 30 7c424 ? 30 7c425 ? 30 7c429 ? 30 7c433 ? 30 7c419 ? 40 7c420 ? 40 7c421 ? 40 7c424 ? 40 7c425 ? 40 7c429 ? 40 7c432 ? 40 7c433 ? 40 7c420 ? 65 7c421 ? 65 7c424 ? 65 7c425 ? 65 7c428 ? 65 7c429 ? 65 7c433 ? 65 parameter description test conditions min. max. min. max. min. max. units i cc operating current v cc = max., i out = 0 ma f = f max com ? l 40 35 35 ma mil/ind 75 70 65 i cc1 operating current v cc = max., i out = 0 ma f = 20 mhz com ? l 35 35 35 ma i sb1 standby current all inputs = v ih min. com ? l 10 10 10 ma mil 15 15 15 i sb2 power-down current all inputs > v cc ? 0.2v com ? l 5 5 5 ma mil 8 8 8 capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 4.5v 6 pf c out output capacitance 6 pf note: 5. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms 3.0v 5v output r1 500 ? r2 333 ? 30 pf including jigand scope gnd 90% 10% 90% 10% 3ns 3 ns 5v output r1 500 ? r2 333 ? 5pf including jigand scope output 2v equivalent to: th venin equivalent (b) c420 ? 6 c420 ? 7 c420 ? 8 (a) all input pulses 200 ?
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 5 of 22 switching characteristics over the operating range [6, 7] 7c419 ? 10 7c421 ? 10 7c425 ? 10 7c429 ? 10 7c433 ? 10 7c419 ? 15 7c421 ? 15 7c425 ? 15 7c429 ? 15 7c433 ? 15 7c420 ? 20 7c421 ? 20 7c424 ? 20 7c425 ? 20 7c428 ? 20 7c429 ? 20 7c433 ? 20 7c420 ? 25 7c421 ? 25 7c424 ? 25 7c425 ? 25 7c429 ? 25 7c432 ? 25 7c433 ? 25 parameter description min. max. min. max. min. max. min. max. unit t rc read cycle time 20 25 30 35 ns t a access time 10 15 20 25 ns t rr read recovery time 10 10 10 10 ns t pr read pulse width 10 15 20 25 ns t lzr [5,8] read low to low z 3 3 3 3 ns t dvr [8,9] data valid after read high 5 5 5 5 ns t hzr [5,8,9] read high to high z 15 15 15 18 ns t wc write cycle time 20 25 30 35 ns t pw write pulse width 10 15 20 25 ns t hwz [5,8] write high to low z 5 5 5 5 ns t wr write recovery time 10 10 10 10 ns t sd data set-up time 6 8 12 15 ns t hd data hold time 0 0 0 0 ns t mrsc mr cycle time 20 25 30 35 ns t pmr mr pulse width 10 15 20 25 ns t rmr mr recovery time 10 10 10 10 ns t rpw read high to mr high 10 15 20 25 ns t wpw write high to mr high 10 15 20 25 ns t rtc retransmit cycle time 20 25 30 35 ns t prt retransmit pulse width 10 15 20 25 ns t rtr retransmit recovery time 10 10 10 10 ns notes: 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v and output loading of the spec ified i ol /i oh and 30 pf load capacitance, as in part (a) of ac test load and waveforms, unless otherwise specified. 7. see the last page of this specification for group a subgroup testing information. 8. t hzr transition is measured at +200 mv from v ol and ? 200 mv from v oh . t dvr transition is measured at the 1.5v level. t hwz and t lzr transition is measured at 100 mv from the steady state. 9. t hzr and t dvr use capacitance loading as in part (b) of ac test load and waveforms.
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 6 of 22 t efl mr to ef low 20 25 30 35 ns t hfh mr to hf high 20 25 30 35 ns t ffh mr to ff high 20 25 30 35 ns t ref read low to ef low 10 15 20 25 ns t rff read high to ff high 10 15 20 25 ns t wef write high to ef high 10 15 20 25 ns t wff write low to ff low 10 15 20 25 ns t whf write low to hf low 10 15 20 25 ns t rhf read high to hf high 10 15 20 25 ns t rae effective read from write high 10 15 20 25 ns t rpe effective read pulse width after ef high 10 15 20 25 ns t waf effective write from read high 10 15 20 25 ns t wpf effective write pulse width after ff high 10 15 20 25 ns t xol expansion out low delay from clock 10 15 20 25 ns t xoh expansion out high delay from clock 10 15 20 25 ns switching characteristics over the operating range [6, 7] (continued) 7c419 ? 10 7c421 ? 10 7c425 ? 10 7c429 ? 10 7c433 ? 10 7c419 ? 15 7c421 ? 15 7c425 ? 15 7c429 ? 15 7c433 ? 15 7c420 ? 20 7c421 ? 20 7c424 ? 20 7c425 ? 20 7c428 ? 20 7c429 ? 20 7c433 ? 20 7c420 ? 25 7c421 ? 25 7c424 ? 25 7c425 ? 25 7c429 ? 25 7c432 ? 25 7c433 ? 25 parameter description min. max. min. max. min. max. min. max. unit
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 7 of 22 switching characteristics over the operating range [6, 7] (continued) 7c419 ? 30 7c421 ? 30 7c424 ? 30 7c425 ? 30 7c429 ? 30 7c433 ? 30 7c419 ? 40 7c420 ? 40 7c421 ? 40 7c424 ? 40 7c425 ? 40 7c429 ? 40 7c432 ? 40 7c433 ? 40 7c420 ? 65 7c421 ? 65 7c424 ? 65 7c425 ? 65 7c428 ? 65 7c429 ? 65 7c433 ? 65 parameter description min. max. min. max. min. max. unit t rc read cycle time 40 50 80 ns t a access time 30 40 65 ns t rr read recovery time 10 10 15 ns t pr read pulse width 30 40 65 ns t lzr [5,8] read low to low z 3 3 3 ns t dvr [8,9] data valid after read high 5 5 5 ns t hzr [5,8,9] read high to high z 20 20 20 ns t wc write cycle time 40 50 80 ns t pw write pulse width 30 40 65 ns t hwz [5,8] write high to low z 5 5 5 ns t wr write recovery time 10 10 15 ns t sd data set-up time 18 20 30 ns t hd data hold time 0 0 0 ns t mrsc mr cycle time 40 50 80 ns t pmr mr pulse width 30 40 65 ns t rmr mr recovery time 10 10 15 ns t rpw read high to mr high 30 40 65 ns t wpw write high to mr high 30 40 65 ns t rtc retransmit cycle time 40 50 80 ns t prt retransmit pulse width 30 40 65 ns t rtr retransmit recovery time 10 10 15 ns t efl mr to ef low 40 50 80 ns t hfh mr to hf high 40 50 80 ns t ffh mr to ff high 40 50 80 ns t ref read low to ef low 30 35 60 ns t rff read high to ff high 30 35 60 ns t wef write high to ef high 30 35 60 ns t wff write low to ff low 30 35 60 ns t whf write low to hf low 30 35 60 ns t rhf read high to hf high 30 35 60 ns t rae effective read from write high 30 35 60 ns t rpe effective read pulse width after ef high 30 40 65 ns t waf effective write from read high 30 35 60 ns t wpf effective write pulse width after ff high 30 40 65 ns t xol expansion out low delay from clock 30 40 65 ns t xoh expansion out high delay from clock 30 40 65 ns
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 8 of 22 switching waveforms notes: 10. w and r v ih around the rising edge of mr . 11. t mrsc = t pmr + t rmr . data valid data valid data valid data valid asynchronous read and write t sd t hd t rc t pr t a t rr t a t lzr t dvr t hzr t wc t pw t wr r q 0 ? q 8 w d 0 ? d 8 master reset mr r ,w hf ff ef t mrsc t pmr t efl t hfh t ffh t rpw t wpw t rmr half full+1 half full half full w r hf t whf t rhf half-full flag c420 ? 9 c420 ? 10 c420 ? 11 [10] [11]
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 9 of 22 notes: 12. ef , hf and ff may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t rtc . 13. t rtc = t prt + t rtr . switching waveforms (continued) last write to first read full flag last read to first write empty flag c420 ? 12 c420 ? 13 c420 ? 14 last write first read additional reads first write valid last read first write additional writes first read valid t ref t wef t rtc t prt t rtr t wff t rff t a w r ef r w ff data out fl /rt r ,w retransmit [12] [13]
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 10 of 22 switching waveforms (continued) empty flag and read data flow-through mode full flag and write data flow-through mode c420 ? 15 c420 ? 16 r w ff w r ef data in data out data in data out data valid data valid data valid t rae t ref t wef t hwz t a t waf t wpf t wff t rff t sd t hd t a t rpe
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 11 of 22 architecture the cy7c419, cy7c420/1, cy7c424/5, cy7c428/9, cy7c432/3 fifos consist of an array of 256, 512, 1024, 2048, 4096 words of 9 bits each (implemented by an array of du- al-port ram cells), a read pointer, a write pointer, control sig- nals (w , r , xi , xo , fl , rt , mr ), and full, half full, and empty flags. dual-port ram the dual-port ram architecture refers to the basic memory cell used in the ram. the cell itself enables the read and write operations to be independent of each other, which is neces- sary to achieve truly asynchronous operation of the inputs and outputs. a second benefit is that the time required to increment the read and write pointers is much less than the time that would be required for data propagation through the memory, which would be the case if the memory were implemented using the conventional register array architecture. resetting the fifo upon power-up, the fifo must be reset with a master reset (mr ) cycle. this causes the fifo to enter the empty condition signified by the empty flag (ef ) being low, and both the half full (hf ) and full flags (ff ) being high. read (r ) and write (w ) must be high t rpw /t wpw before and t rmr after the rising edge of mr for a valid reset cycle. if reading from the fifo after a reset cycle is attempted, the outputs will all be in the high-impedance state. note: 14. expansion out of device 1 (xo 1 ) is connected to expansion in of device 2 (xi 2 ). switching waveforms (continued) expansion timing diagrams c420 ? 17 r w xo 1 (xi 2 ) d 0 ? d 8 data valid data data valid valid t xol t xoh t hd t sd t sd t hd t xol t lzr t a t dvr t xoh t a t dvr t hzr xo 1 (xi 2 ) q 0 ? q 8 write to last physical location of device 1 write to first physical location of device 2 read from last physical location of device 1 read from first physical location of device 2 c420 ? 18 t wr t rr data valid [14] [14]
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 12 of 22 writing data to the fifo the availability of at least one empty location is indicated by a high ff . the falling edge of w initiates a write cycle. data appearing at the inputs (d 0 ? d 8 ) t sd before and t hd after the rising edge of w will be stored sequentially in the fifo. the ef low-to-high transition occurs t wef after the first low-to-high transition of w for an empty fifo. hf goes low t whf after the falling edge of w following the fifo actu- ally being half full. therefore, the hf is active once the fifo is filled to half its capacity plus one word. hf will remain low while less than one half of total memory is available for writing. the low-to-high transition of hf occurs t rhf after the rising edge of r when the fifo goes from half full +1 to half full. hf is available in standalone and width expansion modes. ff goes low t wff after the falling edge of w , during the cycle in which the last available location is filled. internal logic prevents overrunning a full fifo. writes to a full fifo are ignored and the write pointer is not incremented. ff goes high trff after a read from a full fifo. reading data from the fifo the falling edge of r initiates a read cycle if the ef is not low. data outputs (q 0 ? q 8 ) are in a high-impedance condition be- tween read operations (r high), when the fifo is empty, or when the fifo is not the active device in the depth expansion mode. when one word is in the fifo, the falling edge of r initiates a high-to-low transition of ef . the rising edge of r causes the data outputs to go to the high-impedance state and remain such until a write is performed. reads to an empty fifo are ignored and do not increment the read pointer. from the empty condition, the fifo can be read t wef after a valid write. the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit (rt ) input is active in the standalone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred since the last mr cycle. a low pulse on rt resets the internal read pointer to the first physical location of the fifo. r and w must both be high while and t rtr after retransmit is low. with every read cycle after retransmit, pre- viously accessed data as well as not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. full, half full, and empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after activation of rt are transmitted also. up to the full depth of the fifo can be repeatedly retransmit- ted. standalone/width expansion modes standalone and width expansion modes are set by grounding expansion in (xi ) and tying first load (fl ) to v cc . fifos can be expanded in width to provide word widths greater than nine in increments of nine. during width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. depth expansion mode (see figure 1 ) depth expansion mode is entered when, during a mr cycle, expansion out (xo ) of one device is connected to expansion in (xi ) of the next device, with xo of the last device connected to xi of the first device. in the depth expansion mode the first load (fl ) input, when grounded, indicates that this part is the first to be loaded. all other devices must have this pin high. to enable the correct fifo, xo is pulsed low when the last physical location of the previous fifo is written to and pulsed low again when the last physical location is read. only one fifo is enabled for read and one for write at any given time. all other devices are in standby. fifos can also be expanded simultaneously in depth and width. consequently, any depth or width fifo can be created of word widths in increments of 9. when expanding in depth, a composite ff must be created by oring the ff s together. likewise, a composite ef is created by oring the ef s togeth- er. hf and rt functions are not available in depth expansion mode. use of the empty and full flags in order to achieve the maximum frequency, the flags must be valid at the beginning of the next cycle. however, because they can be updated by either edge of the read of write signal, they must be valid by one-half of a cycle. cypress fifos meet this requirement; some competitors ? fifos do not. the reason why the flags are required to be valid by the next cycle is fairly complex. it has to do with the ? effective pulse width violation ? phenomenon, which can occur at the full and empty boundary conditions, if the flags are not properly used. the empty flag must be used to prevent reading from an empty fifo and the full flag must be used to prevent writing into a full fifo. for example, consider an empty fifo that is receiving read pulses. because the fifo is empty, the read pulses are ig- nored by the fifo, and nothing happens. next, a single word is written into the fifo, with a signal that is asynchronous to the read signal. the (internal) state machine in the fifo goes from empty to empty+1. however, it does this asynchronously with respect to the read signal, so that it cannot be determined what the effective pulse width of the read signal is, because the state machine does not look at the read signal until it goes to the empty+1 state. in a similar manner, the minimum write pulse width may be violated by attempting to write into a full fifo, and asynchronously performing a read. the empty and full flags are used to avoid these effective pulse width viola- tions, but in order to do this and operate at the maximum fre- quency, the flag must be valid at the beginning of the next cycle.
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 13 of 22 figure 1. depth expansion cy7c419 cy7c420/1 cy7c424/5 cy7c428/9 cy7c432/3 w mr xi fl ef xo ff xi fl ef xo xi fl ef xo ff r empty full q 9 9 9 9 ff v cc * first device * c420 ? 19 9 cy7c419 cy7c420/1 cy7c424/5 cy7c428/9 cy7c432/3 cy7c419 cy7c420/1 cy7c424/5 cy7c428/9 cy7c432/3 d
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 14 of 22 ordering information speed (ns) ordering code package type package type operating range 10 cy7c419 ? 10ac a32 32-pin thin plastic quad flatpack commercial cy7c419 ? 10jc j65 32-lead plastic leaded chip carrier cy7c419 ? 10pc p21 28-lead (300-mil) molded dip cy7c419 ? 10vc v21 28-lead (300-mil) molded soj 15 cy7c419 ? 15ac a32 32-pin thin plastic quad flatpack commercial cy7c419 ? 15jc j65 32-lead plastic leaded chip carrier cy7c419 ? 15vc v21 28-lead (300-mil) molded soj cy7c419 ? 15ji j65 32-lead plastic leaded chip carrier industrial 30 cy7c419 ? 30jc j65 32-lead plastic leaded chip carrier commercial 40 cy7c419 ? 40ac a32 32-pin thin plastic quad flatpack cy7c419 ? 40jc j65 32-lead plastic leaded chip carrier ordering information (continued) speed (ns) ordering code package type package type operating range 25 cy7c420 ? 25pc p15 28-lead (600-mil) molded dip commercial 40 cy7c420 ? 40pc p15 28-lead (600-mil) molded dip 65 cy7c420 ? 65pc p15 28-lead (600-mil) molded dip ordering information (continued) speed (ns) ordering code package type package type operating range 10 cy7c421 ? 10ac a32 32-pin thin plastic quad flatpack commercial cy7c421 ? 10jc j65 32-lead plastic leaded chip carrier cy7c421 ? 10pc p21 28-lead (300-mil) molded dip cy7c421 ? 10vc v21 28-lead (300-mil) molded soj 15 cy7c421 ? 15ac a32 32-pin thin plastic quad flatpack commercial cy7c421 ? 15jc j65 32-lead plastic leaded chip carrier cy7c421 ? 15ji j65 32-lead plastic leaded chip carrier industrial cy7c421 ? 15vi v21 28-lead (300-mil) molded soj cy7c421 ? 15dmb d22 28-lead (300-mil) cerdip military cy7c421 ? 15lmb l55 32-pin rectangular leadless chip carrier 20 cy7c421 ? 20jc j65 32-lead plastic leaded chip carrier commercial cy7c421 ? 20pc p21 28-lead (300-mil) molded dip cy7c421 ? 20vc v21 28-lead (300-mil) molded soj cy7c421 ? 20ji j65 32-lead plastic leaded chip carrier industrial 25 cy7c421 ? 25jc j65 32-lead plastic leaded chip carrier commercial cy7c421 ? 25pc p21 28-lead (300-mil) molded dip cy7c421 ? 25vc v21 28-lead (300-mil) molded soj cy7c421 ? 25ji j65 32-lead plastic leaded chip carrier industrial cy7c421 ? 25pi p21 28-lead (300-mil) molded dip cy7c421 ? 25dmb d22 28-lead (300-mil) cerdip military 30 cy7c421 ? 30jc j65 32-lead plastic leaded chip carrier commercial cy7c421 ? 30pc p21 28-lead (300-mil) molded dip
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 15 of 22 30 cy7c421 ? 30ji j65 32-lead plastic leaded chip carrier industrial cy7c421 ? 30dmb d22 28-lead (300-mil) cerdip military cy7c421 ? 30lmb l55 32-pin rectangular leadless chip carrier 40 cy7c421 ? 40jc j65 32-lead plastic leaded chip carrier commercial cy7c421 ? 40pc p21 28-lead (300-mil) molded dip cy7c421 ? 40vc v21 28-lead (300-mil) molded soj cy7c421 ? 40ji j65 32-lead plastic leaded chip carrier industrial 65 cy7c421 ? 65jc j65 32-lead plastic leaded chip carrier commercial cy7c421 ? 65pc p21 28-lead (300-mil) molded dip cy7c421 ? 65vc v21 28-lead (300-mil) molded soj cy7c421 ? 65ji j65 32-lead plastic leaded chip carrier industrial cy7c421 ? 65dmb d22 28-lead (300-mil) cerdip military ordering information (continued) speed (ns) ordering code package type package type operating range ordering information (continued) speed (ns) ordering code package type package type operating range 40 cy7c424 ? 40pc p15 28-lead (600-mil) molded dip commercial 65 cy7c424 ? 65pc p15 28-lead (600-mil) molded dip commercial ordering information (continued) speed (ns) ordering code package type package type operating range 10 cy7c425 ? 10ac a32 32-pin thin plastic quad flatpack commercial cy7c425 ? 10jc j65 32-lead plastic leaded chip carrier cy7c425 ? 10pc p21 28-lead (300-mil) molded dip cy7c425 ? 10vc v21 28-lead (300-mil) molded soj 15 cy7c425 ? 15jc j65 32-lead plastic leaded chip carrier commercial cy7c425 ? 15pc p21 28-lead (300-mil) molded dip cy7c425 ? 15dmb d22 28-lead (300-mil) cerdip military cy7c425 ? 15lmb l55 32-pin rectangular leadless chip carrier 20 cy7c425 ? 20jc j65 32-lead plastic leaded chip carrier commercial cy7c425 ? 20pc p21 28-lead (300-mil) molded dip cy7c425 ? 20vc v21 28-lead (300-mil) molded soj 25 cy7c425 ? 25jc j65 32-lead plastic leaded chip carrier commercial cy7c425 ? 25pc p21 28-lead (300-mil) molded dip cy7c425 ? 25ji j65 32-lead plastic leaded chip carrier industrial cy7c425 ? 25vi v21 28-lead (300-mil) molded soj cy7c425 ? 25dmb d22 28-lead (300-mil) cerdip military cy7c425 ? 25lmb l55 32-pin rectangular leadless chip carrier 30 cy7c425 ? 30jc j65 32-lead plastic leaded chip carrier commercial cy7c425 ? 30pc p21 28-lead (300-mil) molded dip cy7c425 ? 30vc v21 28-lead (300-mil) molded soj cy7c425 ? 30vi v21 28-lead (300-mil) molded soj industrial
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 16 of 22 40 cy7c425 ? 40jc j65 32-lead plastic leaded chip carrier commercial cy7c425 ? 40pc p21 28-lead (300-mil) molded dip cy7c425 ? 40vc v21 28-lead (300-mil) molded soj cy7c425 ? 40ji j65 32-lead plastic leaded chip carrier industrial 65 cy7c425 ? 65jc j65 32-lead plastic leaded chip carrier commercial cy7c425 ? 65pc p21 28-lead (300-mil) molded dip ordering information (continued) speed (ns) ordering code package type package type operating range ordering information (continued) speed (ns) ordering code package type package type operating range 20 cy7c428 ? 20pc p15 28-lead (600-mil) molded dip commercial 25 cy7c428 ? 25dmb d16 28-lead (600-mil) cerdip military 65 cy7c428 ? 65pc p15 28-lead (600-mil) molded dip commercial ordering information (continued) speed (ns) ordering code package type package type operating range 10 cy7c429 ? 10ac a32 32-pin thin plastic quad flatpack commercial cy7c429 ? 10jc j65 32-lead plastic leaded chip carrier cy7c429 ? 10pc p21 28-lead (300-mil) molded dip 15 cy7c429 ? 15jc j65 32-lead plastic leaded chip carrier commercial cy7c429 ? 15ji j65 32-lead plastic leaded chip carrier industrial cy7c429 ? 15dmb d22 28-lead (300-mil) cerdip military cy7c429 ? 15lmb l55 32-pin rectangular leadless chip carrier 20 cy7c429 ? 20jc j65 32-lead plastic leaded chip carrier commercial cy7c429 ? 20pc p21 28-lead (300-mil) molded dip cy7c429 ? 20vc v21 28-lead (300-mil) molded soj cy7c429 ? 20dmb d22 28-lead (300-mil) cerdip military 25 cy7c429 ? 25jc j65 32-lead plastic leaded chip carrier commercial cy7c429 ? 25pc p21 28-lead (300-mil) molded dip cy7c429 ? 25vc v21 28-lead (300-mil) molded soj cy7c429 ? 25ji j65 32-lead plastic leaded chip carrier industrial cy7c429 ? 25dmb d22 28-lead (300-mil) cerdip military cy7c429 ? 25lmb l55 32-pin rectangular leadless chip carrier 30 cy7c429 ? 30jc j65 32-lead plastic leaded chip carrier commercial cy7c429 ? 30pc p21 28-lead (300-mil) molded dip cy7c429 ? 30vc v21 28-lead (300-mil) molded soj cy7c429 ? 30dmb d22 28-lead (300-mil) cerdip military 40 cy7c429 ? 40ac a32 32-pin thin plastic quad flatpack commercial cy7c429 ? 40jc j65 32-lead plastic leaded chip carrier cy7c429 ? 40pc p21 28-lead (300-mil) molded dip 65 cy7c429 ? 65jc j65 32-lead plastic leaded chip carrier commercial cy7c429 ? 65pc p21 28-lead (300-mil) molded dip cy7c429 ? 65ji j65 32-lead plastic leaded chip carrier industrial
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 17 of 22 ordering information (continued) speed (ns) ordering code package name package type operating range 25 cy7c432 ? 25pc p15 28-lead (600-mil) molded dip commercial 40 cy7c432 ? 40pc p15 28-lead (600-mil) molded dip commercial ordering information (continued) speed (ns) ordering code package name package type operating range 10 cy7c433 ? 10ac a32 32-pin thin plastic quad flatpack commercial cy7c433 ? 10jc j65 32-lead plastic leaded chip carrier cy7c433 ? 10pc p21 28-lead (300-mil) molded dip cy7c433 ? 10vc v21 28-lead (300-mil) molded soj 15 cy7c433 ? 15ac a32 32-pin thin plastic quad flatpack commercial cy7c433 ? 15jc j65 32-lead plastic leaded chip carrier cy7c433 ? 15ji j65 32-lead plastic leaded chip carrier industrial cy7c433 ? 15pi p21 28-lead (300-mil) molded dip cy7c433 ? 15dmb d22 28-lead (300-mil) cerdip military cy7c433 ? 15lmb l55 32-pin rectangular leadless chip carrier 20 cy7c433 ? 20ac a32 32-pin thin plastic quad flatpack commercial cy7c433 ? 20jc j65 32-lead plastic leaded chip carrier cy7c433 ? 20pc p21 28-lead (300-mil) molded dip 25 cy7c433 ? 25jc j65 32-lead plastic leaded chip carrier commercial cy7c433 ? 25pc p21 28-lead (300-mil) molded dip cy7c433 ? 25vc v21 28-lead (300-mil) molded soj cy7c433 ? 25ji j65 32-lead plastic leaded chip carrier industrial 30 cy7c433 ? 30jc j65 32-lead plastic leaded chip carrier commercial cy7c433 ? 30pc p21 28-lead (300-mil) molded dip cy7c433 ? 30ji j65 32-lead plastic leaded chip carrier industrial cy7c433 ? 30pi p21 28-lead (300-mil) molded dip cy7c433 ? 30dmb d22 28-lead (300-mil) cerdip military cy7c433 ? 30lmb l55 32-pin rectangular leadless chip carrier 40 cy7c433 ? 40jc j65 32-lead plastic leaded chip carrier commercial cy7c433 ? 40pc p21 28-lead (300-mil) molded dip cy7c433 ? 40vc v21 28-lead (300-mil) molded soj cy7c433 ? 40ji j65 32-lead plastic leaded chip carrier industrial 65 cy7c433 ? 65jc j65 32-lead plastic leaded chip carrier commercial cy7c433 ? 65pc p21 28-lead (300-mil) molded dip
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 18 of 22 military specifications group a subgroup testing dc characteristics parameters subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il max. 1, 2, 3 i ix 1, 2, 3 i cc 1, 2, 3 i cc1 1, 2, 3 i sb1 1, 2, 3 i sb2 1, 2, 3 i os 1, 2, 3 switching characteristics parameters subgroups t rc 9, 10, 11 t a 9, 10, 11 t rr 9, 10, 11 t pr 9, 10, 11 t dvr 9, 10, 11 t wc 9, 10, 11 t pw 9, 10, 11 t wr 9, 10, 11 t sd 9, 10, 11 t hd 9, 10, 11 t mrsc 9, 10, 11 t pmr 9, 10, 11 t rmr 9, 10, 11 t rpw 9, 10, 11 t wpw 9, 10, 11 t rtc 9, 10, 11 t prt 9, 10, 11 t rtr 9, 10, 11 t efl 9, 10, 11 t hfh 9, 10, 11 t ffh 9, 10, 11 t ref 9, 10, 11 t rff 9, 10, 11 t wef 9, 10, 11 t wff 9, 10, 11 t whf 9, 10, 11 t rhf 9, 10, 11 t rae 9, 10, 11 t rpe 9, 10, 11 t waf 9, 10, 11 t wpf 9, 10, 11 t xol 9, 10, 11 t xoh 9, 10, 11
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 19 of 22 package diagrams 32-lead thin plastic quad flat pack a32 28-lead (600-mil) cerdip d16 mil-std-1835 d- 10config.a 28-lead (300-mil) cerdip d22 mil-std-1835 d- 15 config.a
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 20 of 22 package diagrams (continued) 32-lead plastic leaded chip carrier j65 32-pin rectangular leadless chip carrier l55 mil-std-1835 c-12 28-lead (600-mil) molded dip p15
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 21 of 22 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-lead (300-mil) molded dip p21 28-lead (300-mil) molded soj v21
cy7c419/21/25/29/33 document #: 38-06001 rev. ** page 22 of 22 document title: cy7c419, cy7c421, cy7c425, cy7c429, cy7c433 256/512/1k/2k/4kx9 asynchronous fifo document number: 38-06001 rev. ecn no. issue date orig. of change description of change ** 106462 07/11/01 szv change from spec number: 38-00079 to 38-06001

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